In a semiconductor memory, owing to the reduction of voltage in a system, the importance is how the semiconductor memory is operated in such a manner that a data sense speed is not reduced. It should be here noted that the thinner gate insulating film thickness of a cell transistor of a memory cell allows the voltage to be reduced at a boot level of a word line. However, on the other hand, the allowable minimum threshold voltage of the memory cell is little changed between generations.
FIG. 1 is a waveform chart of the word line and bit line associated with a read operation of a conventional DRAM (Dynamic RAM). When the reduced voltage in a system is not significant in a DRAM, a boot voltage of Vw1h1 of a word line WL is sufficiently high with reference to specifications. In this case, the drop (Vth) of the threshold voltage of the memory cell to be turned on has no adverse effect on the sense speed during the read operation. This will be described below.
In FIG. 1, a possible maximum value Vsn(1)max of a potential at "H" (high) level of a storage node of the memory cell is specified by the word line boot voltage (Vw1h1). That is, this maximum value is a: such a level that the boot voltage Vw1h1 is dropped by the threshold voltage (Vth) of the memory cell.
The "H" potential (Vb1h) of the read bit line can be set so that it may be equal to or less than the "H" potential of the memory cell. Namely, Vsn(1)max.gtoreq.Vb1h, consequently resulting in Vb1h=Vsn(1) (Vsn(1) corresponds to the value which is determined as the "H" potential of the storage node of the memory cell (.ltoreq.Vsn(1)max)). Thus, a reference bit line potential (Vb1h/2) for equalizing (or precharging) also supplies a sufficient potential to exhibit driving capability in a sense amplifier, which makes a high-speed read operation possible (in equations in the drawings, Cb denotes a bit line capacity and Cs denotes a storage capacity of the memory cell).
That is, the bit line potential on the side of the sense amplifier is linked to the storage node of the memory cell having the potential Vsn(0) or Vsn(1) corresponding to holding data. The bit line potential on the side of the sense is changed from an equalizing potential (Vb1h/2) into a sense potential (VBL(0) or VBL(1)). Here is shown that the potential of the storage node linked to the bit line is also changed into the sense potential. After that, this sense potential is sense-amplified, compared with the reference bit line potential, that is, Vb1h/2, whereby the sense potential is then read as memory cell data.
The operation of the sense amplification will be simply described below. FIG. 3 is a circuit diagram of the sense amplifier. In the drawing, it is assumed that BL denotes a sense potential VBL(1) and /BL denotes an equalizing potential 1/2Vb1h. In this state, a sense amplifier drive line/SAN is changed from 1/2Vb1h into 0 V. Then, since the gate potential of an NMOS transistor Q2 is higher than that of an NMOS transistor Q1, the current driving rate of the NMOS transistor Q2 is higher than that of the NMOS transistor Q1. Therefore, the potential of /BL is reduced and becomes equal to the potential 0 V of /SAN. On the other hand, when the sense amplifier drive line SAP is changed from 1/2Vb1h into Vb1h, since the gate potential of a PMOS transistor Q3 is lower than that of a PMOS transistor Q4, the current driving rate of the PMOS transistor Q3 is higher than that of the PMOS transistor Q4. Therefore, the potential of SL is increased and becomes equal to the potential Vb1h of SAP.
In the above-described DRAM, a potential difference is made between the "L" potential Vsn(0) and the "H" potential Vsn(1) in the storage node of the memory cell where this potential difference is provided such as set sense speed at which sense data is not hindered at the time of read the memory cell. Therefore, in general, the "H" potential (Vb1h) of the bit line during read has a specification in which it is set equally to the "H" potential of the memory cell without any trouble.
However, in the case of the DRAM in which the voltage is considerably reduced in the system, as illustrated by the waveform chart shown in FIG. 2, the drop (Vth) of the threshold voltage of the memory cell has an adverse effect on the sense speed at the time of read. Next, this will be described below.
In FIG. 2, a boot voltage Vw1h2 of the word line WL is set so that it may be still lower than the boot voltage Vw1h1 of FIG. 1. Due to the same effect of the drop (Vth) of the threshold voltage of the memory cell as described above, a possible maximum value Vsn(1)max of the "H" potential of the memory cell is also reduced. As shown in FIG. 2, the "H" potential (Vb1h) of the bit line is generally set so that it may be equal to or less than the maximum value Vsn(1)max of the "H" potential of the memory cell. Therefore, the reference bit line potential (Vb1h/2) is also lower than the reference bit line potential of FIG. 1.
As a result, the sense speed is reduced at the time of read. That is, the potential (Vb1h) of an operating power source supplied to the sense amplifier shown in FIG. 3, the reference bit line potential Vb1h/2 and the sense potential (VBL(0) or VBL(1)) of the bit line are at low level as a whole. Thus, since the potential difference between VBL(1) and Vb1h/2 and the potential difference between VBL(0) and Vb1h/2 are reduced, due to the difference between MOS transistors Q1 and Q2 in current driving capability, the sense operation is prone to a faulty operation. Moreover, the reduction of the reference bit line potential causes the decrease of the potential between the gate and source of the MOS transistor in the sense amplifier. Consequently, the driving capability of a MOS transistor in the sense amplifier is deteriorated and thus the amplification is slowly operated.
Accordingly, This is feared that reliability is considerably reduced in the read operation in a sense system circuit.